A 4.2-pJ/conv 10-b Asynchronous ADC with Hybrid Two-tier Level-crossing Event Coding

Abstract

An asynchronous continuous-time level-crossing analog-to-digital converter (LC-ADC) for high-throughput, high resolution applications is presented. The proposed 10-bit ADC architecture comprises two stages of level-crossing ADCs, the first stage resolving for 5 MSBs and the second folded residue stage for 5 LSBs. Gray encoding of the output bits ensure single bit transitions between adjacent digital outputs. Compared to uniform-sampling synchronous ADCs, LC-ADCs generate fewer samples for sparse signals, useful in many applications for biomedical signal acquisition, event-driven computer vision, etc. Unlike conventional LC-ADCs with a few comparators tuned for lower power consumption to acquire sparse signals, this two-tier LC-ADC is optimized for high-resolution tracking of continuous signals, like Electrocardiogram (ECG). Designed and fabricated in 0.18-mu m CMOS technology, chip area of the proposed ADC is 1310 x 125 mu m(2). Operating at 1.8 V supply, the ADC consumes 160-426 mu W for 1 Hz to 200 kHz input frequencies at full scale amplitude and achieves an energy efficiency figure-of-merit of 4.16-pJ/conv.