Double-layered vertically integrated amorphous-In2Ga2ZnO7 thin-film transistor

Abstract

Two serially connected and vertically integrated amorphous-In2Ga2ZnO7 thin film transistors (V-TFTs) with similar to 600 and 400-nm channel lengths were fabricated. Top and bottom V-TFTs showed well-behaved transfer characteristics with an I-on/I-off ratio of similar to 10(8) and a sub-threshold swing of similar to 0.6 V/dec., which are much improved results compared with the previous report on single-layer V-TFTs. Electrical performances of two V-TFTs were cross-checked, and they showed certain influences from the other device depending on operation conditions, which was attributed to charge trapping in the gate dielectric layer during gate voltage sweeping. V-TFT with thermally grown SiO2 showed negligible charge trapping behavior. (C) 2013 AIP Publishing LLC.