A pipelined architecture for VLSI implementation of quantizer/inverse quantizer processor for video CODEC.

Title
A pipelined architecture for VLSI implementation of quantizer/inverse quantizer processor for video CODEC.
Authors
김형곤권용무민남기김재형
Issue Date
1994-10
Publisher
Proceedings of the fifth international conference on signal processing applications & technology (IC
Citation
, 1737-1742
URI
http://pubs.kist.re.kr/handle/201004/21104
Appears in Collections:
KIST Publication > Conference Paper
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