Improved-quality Real-time stereo vision processor

Title
Improved-quality Real-time stereo vision processor
Authors
한상교우성훈정문호유범재
Keywords
stereo vision; ASIC; vision processor
Issue Date
2009-01
Publisher
22nd International Conference on VLSI Design
Citation
, 287-292
Abstract
This paper presents a stereo vision processor with the form of ASIC that achieves enhanced quality depth maps and real-time performance. Our vision processor can be used broadly in practical applications. To improve depth map quality, pre- and post-processing units are adopted, and SFRs (Special Function Registers) are assigned to vision parameters for controllable quality. To meet real-time requirements, the stereo vision system is implemented on hardware using sophisticated design. We integrate image rectification, bilateral filtering, depth estimator and left-right consistency check blocks on a single silicon chip. This processor is fabricated in a 0.18-um standard CMOS technology, and can operate at 120MHz clock frequency achieving over 140 frames/s depth maps with 320 by 240 image size and 64 disparity levels. The system exploits 8-bit sub-pixel disparities for depth accuracy, and shows the throughput over 707 million PDS, which is better than results of any published work. The unrectified and unfiltered images taken at real environment are used as test inputs for performance and quality evaluation. Comparisons with previous ASIC implementations are presented to verify the improvement of this task.
URI
http://pubs.kist.re.kr/handle/201004/36879
Appears in Collections:
KIST Publication > Conference Paper
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