FPGA Design and Implementation of a Real-Time Stereo Vision System

Title
FPGA Design and Implementation of a Real-Time Stereo Vision System
Authors
진승훈조준국팜준타이이경무박성기김문상전재욱
Keywords
stereo vision; real time; disparity; FPGA; Field programmable gate arrays; integrated circuit design; video signal processing
Issue Date
2010-01
Publisher
IEEE transactions on circuits and systems for video technology : a publication of the Circuits and Systems Society
Citation
VOL 20, NO 1, 15-26
Abstract
Stereo vision is a well-known ranging method because it resembles the basic mechanism of the human eye. However, the computational complexity and large amount of data access make real-time processing of stereo vision challenging because of the inherent instruction cycle delay within conventional computers. In order to solve this problem, the past 20 years of research have focused on the use of dedicated hardware architecture for stereo vision. This paper proposes a fully pipelined stereo vision system providing a dense disparity image with additional sub-pixel accuracy in real-time. The entire stereo vision process, such as rectification, stereo matching, and post-processing, is realized using a single field programmable gate array (FPGA) without the necessity of any external devices. The hardware implementation is more than 230 times faster when compared to a software program operating on a conventional computer, and shows stronger performance over previous hardware-related studies.
URI
http://pubs.kist.re.kr/handle/201004/38036
ISSN
1051-8215
Appears in Collections:
KIST Publication > Article
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