Reduction of channel resistance in amorphous oxide thin-film transistors with buried layer
- Reduction of channel resistance in amorphous oxide thin-film transistors with buried layer
- 정유진; 김보슬; 이상렬
- Issue Date
- IOP Conference Series: Materials Science and Engineering
- VOL 34, 012005-1-012005-6
- A silicon-indium-zinc-oxide (SIZO) thin film transistor (TFT) with low channel-resistance (RCH) indium-zinc-oxide (In2O3:ZnO = 9:1) buried layer annealed at low temperature of 200°C exhibited high field-effect mobility (μFE) over 55.8 ㎠/Vs which is 5 times higher than that of the conventional TFTs due to small threshold voltage (Vth) change of 1.8 V under bias-temperature stress (BTS) condition for 420 minutes. The low-RCH buried-layer allows more strong current-path formed in channel layer well within relatively high-RCH channel-layer since it is less affected by the channel bulk and/or back interface trap with high carrier concentration.
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