Modified wirte-and-verify scheme for improving the endurance of multi-level cell phase-change memory using Ge-doped SbTe

Title
Modified wirte-and-verify scheme for improving the endurance of multi-level cell phase-change memory using Ge-doped SbTe
Authors
장강우철정증현정두석유원종정병기
Keywords
Multi-level; phase-change memory; Modified WAV scheme; Endurance improvement
Issue Date
2012-10
Publisher
Solid-state electronics
Citation
VOL 76, 67-70
Abstract
In this study, a modified write-and-verify (WAV) scheme is proposed for improving the programming/ erasing (P/E) endurance of multi-level cell (MLC) phase-change memory (PCM) using Ge-doped SbTe (GeST). A dual reference data read method is developed to detect the level margin decay during P/E cycling, and a trigger condition is designed to trigger self-repair for the degraded cells before any P/E error for the modified WAV scheme. Experimental results suggest that the modified WAV scheme effectively extends the P/E endurance of PCM using GeST during 4-level P/E by at least 10 times. The modified WAV scheme is expected to improve the endurance of MLC–PCM of system applications.
URI
http://pubs.kist.re.kr/handle/201004/42861
ISSN
00381101
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KIST Publication > Article
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