A LOW-POWER HIGH-SPEED PIPELINED PHASE ACCUMULATOR WITH 2-STAGE PRE-SKEWING REGISTERS

Title
A LOW-POWER HIGH-SPEED PIPELINED PHASE ACCUMULATOR WITH 2-STAGE PRE-SKEWING REGISTERS
Authors
Yun-Hwan JungJae-Hun JungJu-Eon Kim이택진우덕하이석Kwang-Hyun Baek
Keywords
Direct Digital Frequency Synthesizer (DDFS); Phase accumulator
Issue Date
2012-10
Publisher
International Technical Conference 2012
Citation
, 1-5
Abstract
This paper presents a low-power high-speed pipelined Phase Accumulator (PACC) for direct digital frequency synthesizers (DDFSs). In order to minimize the number of pre-skewing F/Fs, the designed PACC sequentially loads Frequency Control Word (FCW) input data directly to the corresponding unit accumulators without through series of flip-flops. Simulation results show that the PACC with the 2-stage pre-skewing registers operates at clock frequency of up to 2.5-GHz and reduces power consumption compared to conventional PACC designs.
URI
http://pubs.kist.re.kr/handle/201004/43255
Appears in Collections:
KIST Publication > Conference Paper
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