An FPGA-based Parallel Hardware Architecture for Real-time Eye Detection
- An FPGA-based Parallel Hardware Architecture for Real-time Eye Detection
- 김동현; 정준희; Nguyen, Thuy Tuong; 김대진; 김문상; 권기호; 전재욱
- Eye detection; FPGA; architecture; image processing; HDL; hardware architecture
- Issue Date
- Journal of semiconductor technology and science
- VOL 12, NO 2, 150-161
- Eye detection is widely used in applications, such as face recognition, driver behavior analysis, and human-computer interaction. However, it is difficult to achieve real-time performance with software-based eye detection in an embedded environment. In this paper, we propose a parallel hardware architecture for real-time eye detection. We use the AdaBoost algorithm with modified census transform(MCT) to detect eyes on a face image. We parallelize part of the algorithm to speed up processing. Several downscaled pyramid images of the eye candidate region are generated in parallel using the input face image. We can detect the left and the right eye simultaneously using these downscaled images. The sequential data processing bottleneck caused by repetitive operation is removed by employing a pipelined parallel architecture. The proposed architecture is designed using Verilog HDL and implemented on a Virtex-5 FPGA for prototyping and evaluation. The proposed system can detect eyes within 0.15 ms in a VGA image.
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