3-D Solenoid Inductor Analysis in a 0.13 μm Digital CMOS Technology

Title
3-D Solenoid Inductor Analysis in a 0.13 μm Digital CMOS Technology
Authors
남철이병렬김현철김진석장동욱김봉환
Keywords
solenoid inductor; Voltage Controlled Oscillator; EM simulation
Issue Date
2014-12
Publisher
International Journal of Electronics and Electrical Engineering
Citation
VOL 2, NO 4, 286-290
Abstract
This paper presents the analysis of a small-area on-chip solenoid inductor using the 0.13μm digital CMOS process. The on-chip solenoid inductor is vertically constructed using metal and via layers with a horizontal scalability. This gives the advantage of occupying a small area due to its 3-D structure compared to a spiral inductor. The electrical characteristics of the solenoid inductor have been analyzed by employing 3-D EM simulation. The proposed equivalent model of the solenoid inductor is introduced to get the insight of the scalability so that the selection of the inductance is simply choosing the number of turns. This small area solenoid inductor can be good candidate for LC type VCO for GHz PLL in the standard CMOS process with saving die cost.
URI
http://pubs.kist.re.kr/handle/201004/47431
ISSN
2301380X
Appears in Collections:
KIST Publication > Article
Files in This Item:
There are no files associated with this item.
Export
RIS (EndNote)
XLS (Excel)
XML


qrcode

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

BROWSE