3-D Solenoid Inductor Analysis in a 0.13 μm Digital CMOS Technology
- 3-D Solenoid Inductor Analysis in a 0.13 μm Digital CMOS Technology
- 남철; 이병렬; 김현철; 김진석; 장동욱; 김봉환
- solenoid inductor; Voltage Controlled Oscillator; EM simulation
- Issue Date
- International Journal of Electronics and Electrical Engineering
- VOL 2, NO 4, 286-290
- This paper presents the analysis of a small-area on-chip solenoid inductor using the 0.13μm digital CMOS process. The on-chip solenoid inductor is vertically constructed using metal and via layers with a horizontal scalability. This gives the advantage of occupying a small area due to its 3-D structure compared to a spiral inductor. The electrical characteristics of the solenoid inductor have been analyzed by employing 3-D EM simulation. The proposed equivalent model of the solenoid inductor is introduced to get the insight of the scalability so that the selection of the inductance is simply choosing the number of turns. This small area solenoid inductor can be good candidate for LC type VCO for GHz PLL in the standard CMOS process with saving die cost.
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- KIST Publication > Article
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