Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors
- Direct wafer bonding technology for large-scale InGaAs-on-insulator transistors
- 김상현; Yuki Ikku; Masafumi Yokoyama; Ryosho Nakane; Jian Li; Yung-Chung Kao; Mitsuru Takenaka; Shinichi Takagi
- Issue Date
- Applied physics letters
- VOL 105, NO 4, 043504-1-043504-4
- Heterogeneous integration of III-V devices on Si wafers have been explored for realizing high
device performance as well as merging electrical and photonic applications on the Si platform.
Existing methodologies have unavoidable drawbacks such as inferior device quality or high cost in comparison with the current Si-based technology. In this paper, we present InGaAs-on-insulator (-OI) fabrication from an InGaAs layer grown on a Si donor wafer with a III-V buffer layer instead of growth on a InP donor wafer. This technology allows us to yield large wafer size scalability of III-V-OI layers up to the Si wafer size of 300mm with a high film quality and low cost. The high film quality has been confirmed by Raman and photoluminescence spectra. In addition, the fabricated InGaAs-OI transistors exhibit the high electron mobility of 1700 cm2/V s and uniform distribution of the leakage current, indicating high layer quality with low defect density.
- Appears in Collections:
- KIST Publication > Article
- Files in This Item:
There are no files associated with this item.
- RIS (EndNote)
- XLS (Excel)
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.