Special Memory Mechanisms in SOI Devices

Title
Special Memory Mechanisms in SOI Devices
Authors
S. CristoloveanuM. BawedinC. NavarroS-J. ChangJ. WanF. AndrieuC. Le RoyerN. RodriguezF. GamizA. Zaslavsky김용태
Issue Date
2015-05
Publisher
ECS transactions
Citation
VOL 66, NO 5, 201-210
Abstract
Several types of floating-body capacitorless 1T-DRAM memory cells with planar SOI or multi-gate configuration are reviewed and compared. We show that 1T-DRAMs are also compatible with the ‘unified memory’ paradigm which aims at combining, within a single SOI transistor, volatile, nonvolatile and multiple-state memory functionalities. We focus on our recently proposed concepts (MSDRAM, A2RAM and Z2-FET), by addressing the device architecture and fabrication, operating mechanisms, and scaling issues. Experimental results together with numerical simulations indicate the directions for performance optimization.
URI
http://pubs.kist.re.kr/handle/201004/50282
ISSN
19385862
Appears in Collections:
KIST Publication > Article
Files in This Item:
There are no files associated with this item.
Export
RIS (EndNote)
XLS (Excel)
XML


qrcode

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.

BROWSE