Special Memory Mechanisms in SOI Devices
- Special Memory Mechanisms in SOI Devices
- S. Cristoloveanu; M. Bawedin; C. Navarro; S-J. Chang; J. Wan; F. Andrieu; C. Le Royer; N. Rodriguez; F. Gamiz; A. Zaslavsky; 김용태
- Issue Date
- ECS transactions
- VOL 66, NO 5, 201-210
- Several types of floating-body capacitorless 1T-DRAM memory cells with planar SOI or multi-gate configuration are reviewed and compared. We show that 1T-DRAMs are also compatible with the ‘unified memory’ paradigm which aims at combining, within a single SOI transistor, volatile, nonvolatile and multiple-state memory functionalities. We focus on our recently proposed concepts (MSDRAM, A2RAM and Z2-FET), by addressing the device architecture and fabrication, operating mechanisms, and scaling issues. Experimental results together with numerical simulations indicate the directions for performance optimization.
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