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dc.contributor.authorShinichi Takagi-
dc.contributor.authorRui Zhang-
dc.contributor.authorJunkyo Suh-
dc.contributor.authorMasafumi Yokoyama-
dc.contributor.authorKoichi Nishi-
dc.contributor.authorMitsuru Takenaka-
dc.identifier.citationVOL 54, 06FA01-1-06FA01-18-
dc.description.abstractCMOS utilizing high-mobility III–V/Ge channels on Si substrates is expected to be one of the promising devices for high-performance and low power advanced LSIs in the future, because of its enhanced carrier transport properties. However, there are many critical issues and difficult challenges for realizing III–V/Ge-based CMOS on the Si platform such as (1) the formation of high-crystal-quality Ge/III–V films on Si substrates, (2) gate stack technologies to realize superior MOS/MIS interface quality, (3) the formation of a source/drain (S/D) with low resistivity and low leakage current, (4) process integration to realize ultrashort channel devices, and (5) total CMOS integration including Si CMOS. In this paper, we review the recent progress in III–V/Ge MOS devices and process technologies as viable approaches to solve the above critical problems on the basis of our recent research activities. The technologies include MOS gate stack formation, high-quality channel formation, low-resistance S/D formation, and CMOS integration. For the Ge device technologies, we focus on the gate stack technology and Ge channel formation on Si. Also, for the III–V MOS device technologies, we mainly address the gate stack technology, III–V channel formation on Si, the metal S/D technology, and implementation of these technologies into short-channel III–V-OI MOSFETs on Si substrates. On the basis of the present status of the achievements, we finally discuss the possibility of various CMOS structures using III–V/Ge channels.-
dc.publisherJapanese journal of applied physics-
dc.titleIII-V/Ge channel MOS device technologies in nano CMOS era-
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