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dc.contributor.authorRyo Iida-
dc.contributor.author김상현-
dc.contributor.authorMasafumi Yokoyama-
dc.contributor.authorNoriyuki Taoka-
dc.contributor.authorSangHoon Lee-
dc.contributor.authorMitrusu Takenaka-
dc.contributor.authorShinichi Takagi-
dc.date.accessioned2015-12-03T02:08:55Z-
dc.date.available2015-12-03T02:08:55Z-
dc.date.issued201112-
dc.identifier.citationVOL 100, NO 124505-
dc.identifier.issn00218979-
dc.identifier.other45534-
dc.identifier.urihttp://pubs.kist.re.kr/handle/201004/50948-
dc.description.abstractWe present the operation of planer-type In0.53Ga0.47As- and In0.53Ga0.47As- on-insulator-channel band-to-band-tunneling MOSFETs with Ion/Ioff ratio of 105 in the VG swing of 1.5 V and sub-threshold slope (S.S.) of around 230 mV/dec at room temperature. It is experimentally found that the reduction in equivalent oxide thickness (EOT) of the gate insulators and the increase in the steepness of Be profiles in the source region effectively decrease the S.S. values. The experimental S.S. values at low temperature of 4.2 K amount to 110 and 63 mV/dec for tunneling field-effect transistors (TFET) with the gate insulator EOT of 4.5 and 2.9 nm, respectively. The TFET current has exhibited strong temperature dependence attributable to trap-related leakage current, which significantly degrades the S.S. values around room temperature. On the other hand, the results of the 2-dimensional device simulation show that the S.S. values at 4.2 K can be quantitatively represented by band-to-band tunneling current in the present TFETs. It is shown from the analyses using this device simulation that further improvement of the S.S. value in planar InGaAs TFETs can be realized by the reduction in the defect density, the thinning EOT and the improvement in the steepness of the Be profiles in the source pþ/n junction of TFETs.-
dc.publisherJournal of applied physics-
dc.titlePlanar-type In0.53Ga0.47As channel band-to-band tunneling metal-oxide-semiconductor field-effect transistors-
dc.typeArticle-
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