Extended Analysis of the Z2-FET:Operation as Capacitorless eDRAM

Title
Extended Analysis of the Z2-FET:Operation as Capacitorless eDRAM
Authors
김용태Carlos NavarroJoris LacordMukta Singh PariharFikru Adamu-LemaMeng DuanNoel RodriguezBinjie ChengHassan El DiraniJean-Charles BarbePascal FonteneauMaryline BawedinCampbell MillarPhilippe GalyCyrille Le RoyerSiegfried KargPaul WellsAsen AsenovSorin CristoloveanuFrancisco Gamiz
Keywords
1T-DRAM; capacitorless; feedback effect; fully depleted (FD); ground plane; lifetime; sharp switch; silicon-on-insulator (SOI); Z2-FET
Issue Date
2017-11
Publisher
IEEE transactions on electron devices
Citation
VOL 64, NO 11-4491
Abstract
The Z²-FET operation as capacitorless DRAM is analyzed using advanced 2-D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28-nm fully depleted silicon-on-insulator devices. It is found that the triggering mechanism is dominated by the front-gate bias and the carrier's diffusion length. As in other FB-DRAMs, the memory window is defined by the ON voltage shift with the stored body charge. However, the Z²-FET's memory state is not exclusively defined by the inner charge but also by the reading conditions.
URI
http://pubs.kist.re.kr/handle/201004/66347
ISSN
0018-9383
Appears in Collections:
KIST Publication > Article
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