Z2FET; eDRAM; High Density Integration; 28nm; low power; FD-SOI
IEEE transactions on electron devices
VOL 64, NO 12-4909
2-D numerical simulations are used to demonstrate the Z2-FET as a competitive embedded capacitorless dynamic random access memory cell for low-power applications. Experimental results in 28-nm fully depletedsilicon on insulator technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling
scenarios are considered before comparing the bit cell area consumption and integration density with other eDRAM cells in the literature.