Four-Bits-Per-Cell Operation in an HfO2-Based Resistive Switching Device
- Four-Bits-Per-Cell Operation in an HfO2-Based Resistive Switching Device
- 주현수; 차익수; 김건환; 양민규; 이동규; 최지원; 장재혁; 이상길; 박보근; 한정환; 정택모; 김경민; 황철성; 이영국
- Resistive switching (RS); incremental step pulse programming (ISPP); error
checking/correction (ECC) algorithm; HfO2; quadruple-level cell (QLC)
- Issue Date
- VOL 13, NO 40-1701781-7
- The quadruple-level cell technology is demonstrated in an Au/Al2O3/HfO2/TiN resistance switching memory device using the industry-standard incremental step pulse programming (ISPP) and error checking/correction (ECC) methods. With the highly optimistic properties of the tested device, such as self-compliance and gradual set-switching behaviors, the device shows 6s reliability up to 16 states with a state current gap value of 400 nA for the total allowable programmed current range from 2 to 11 mu A. It is demonstrated that the conventional ISPP/ECC can be applied to such resistance switching memory, which may greatly contribute to the commercialization of the device, especially competitively with NAND flash. A relatively minor improvement in the material and circuitry may enable even a five-bits-per-cell technology, which can hardly be imagined in NAND flash, whose state-of-the-art multiple-cell technology is only at three-level (eight states) to this day.
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