Heterogeneous Integration Toward a Monolithic 3-D Chip Enabled by III-V and Ge Materials

Title
Heterogeneous Integration Toward a Monolithic 3-D Chip Enabled by III-V and Ge Materials
Authors
최원준송진동김형준김상현한재훈이수빈심재필주건우김성광김한성비덴코김호성금대명임희정임형락Chang-Mo KangDong Seon Lee
Issue Date
2018-05
Publisher
IEEE Journal of the Electron Devices Society
Citation
VOL 6, NO 5-587
Abstract
Monolithic 3-D integration has emerged as a promising technological solution for traditional transistor scaling limitations and interconnection bottleneck. The challenge we must overcome is a processing temperature limit for top side devices in order to ensure proper performance of bottom side devices. To solve this problem, we developed a low temperature III– V and Ge layer stacking process using wafer bonding and epitaxial lift-off, since these materials can be processed at a low temperature and provide extended opportunity/functionality (sensor, display, analog, RF, etc.) via heterogeneous integration. In this paper, we discuss technology for integrating III– V and Ge materials and its applicability to CMOS, thin film photodiodes, mid-infrared photonics platforms, and MicroLED display integration for creating the ultimate 3-D chip of the future.
URI
http://pubs.kist.re.kr/handle/201004/67593
ISSN
2168-6734
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KIST Publication > Article
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