Heterogeneous Integration Toward a Monolithic 3-D Chip Enabled by III-V and Ge Materials
- Heterogeneous Integration Toward a Monolithic 3-D Chip Enabled by III-V and Ge Materials
- 최원준; 송진동; 김형준; 김상현; 한재훈; 이수빈; 심재필; 주건우; 김성광; 김한성; 비덴코; 김호성; 금대명; 임희정; 임형락; Chang-Mo Kang; Dong Seon Lee
- Issue Date
- IEEE Journal of the Electron Devices Society
- VOL 6, NO 5-587
- Monolithic 3-D integration has emerged as a promising technological solution for traditional
transistor scaling limitations and interconnection bottleneck. The challenge we must overcome is a processing temperature limit for top side devices in order to ensure proper performance of bottom side devices. To solve this problem, we developed a low temperature III– V and Ge layer stacking process using wafer bonding and epitaxial lift-off, since these materials can be processed at a low temperature and provide extended opportunity/functionality (sensor, display, analog, RF, etc.) via heterogeneous integration. In this paper, we discuss technology for integrating III– V and Ge materials and its applicability to CMOS, thin film photodiodes, mid-infrared photonics platforms, and MicroLED display integration for creating the ultimate 3-D chip of the future.
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