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dc.contributor.author임매순-
dc.contributor.author한진우-
dc.contributor.author이현진-
dc.contributor.author유리은-
dc.contributor.author김성호-
dc.contributor.author김창훈-
dc.contributor.author전상철-
dc.contributor.author김광희-
dc.contributor.author이기성-
dc.contributor.author오재섭-
dc.contributor.author박윤창-
dc.contributor.author이희목-
dc.contributor.author최양규-
dc.date.accessioned2021-06-09T04:24:04Z-
dc.date.available2021-06-09T04:24:04Z-
dc.date.issued2008-01-
dc.identifier.citationVOL 29, NO 1-105-
dc.identifier.issn0741-3106-
dc.identifier.other54513-
dc.identifier.urihttp://pubs.kist.re.kr/handle/201004/71042-
dc.description.abstractAn ultimately scaled multiple-gate CMOS thin-film transistor with a polysilicon (poly-Si) nanowire demonstrates feasibility for vertical integration using multiple active layers for application in the terabit memory era. The short-channel effects are suppressed using a multiple gate to wrap around the nanowire in devices with a size of a few tenths of a nanometer. The switching and output characteristics show high device performance without a crystallization process for the poly-Si nanowire.-
dc.publisherIEEE Electron Device Letters-
dc.titleMultiple-gate CMOS thin-film transistor with polysilicon nanowire-
dc.typeArticle-
dc.relation.page102105-
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