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적층 가능한 비정질 기판 위 III-V 반도체 소자 및 그 제작 방법

Author

주현수; 장준연; 이교섭; 송진동

Assignee

한국과학기술연구원

Regitration Date

2019-02-22

Registration No.

10-1953217

Application Date

2016-08-26

Application No.

2016-0109471

Country

KO

URI

https://pubs.kist.re.kr/handle/201004/83013

Appears in Collections:

KIST Patent > 2016

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