KIM Hyoung Gon Kwon Yong-Moo 민남기 김재형 2024-01-13T22:31:32Z 2024-01-13T22:31:32Z 2021-09-29 https://pubs.kist.re.kr/handle/201004/112120 English A pipelined architecture for VLSI implementation of quantizer/inverse quantizer processor for video CODEC. Conference 1 Proceedings of the fifth international conference on signal processing applications & technology (IC, pp.1737 - 1742 Proceedings of the fifth international conference on signal processing applications & technology (IC 1737 1742 US