Kubendran, Rajkumar Park, Jongkil Sharma, Ritvik Ha, Sohmyung Joshi, Siddharth Cauwenberghs, Gert Kim, Chul 2024-01-19T09:09:24Z 2024-01-19T09:09:24Z 2022-02-26 2020-10 0271-4302 https://pubs.kist.re.kr/handle/201004/113588 An asynchronous continuous-time level-crossing analog-to-digital converter (LC-ADC) for high-throughput, high resolution applications is presented. The proposed 10-bit ADC architecture comprises two stages of level-crossing ADCs, the first stage resolving for 5 MSBs and the second folded residue stage for 5 LSBs. Gray encoding of the output bits ensure single bit transitions between adjacent digital outputs. Compared to uniform-sampling synchronous ADCs, LC-ADCs generate fewer samples for sparse signals, useful in many applications for biomedical signal acquisition, event-driven computer vision, etc. Unlike conventional LC-ADCs with a few comparators tuned for lower power consumption to acquire sparse signals, this two-tier LC-ADC is optimized for high-resolution tracking of continuous signals, like Electrocardiogram (ECG). Designed and fabricated in 0.18-mu m CMOS technology, chip area of the proposed ADC is 1310 x 125 mu m(2). Operating at 1.8 V supply, the ADC consumes 160-426 mu W for 1 Hz to 200 kHz input frequencies at full scale amplitude and achieves an energy efficiency figure-of-merit of 4.16-pJ/conv. English IEEE A 4.2-pJ/conv 10-b Asynchronous ADC with Hybrid Two-tier Level-crossing Event Coding Conference 1 IEEE International Symposium on Circuits and Systems (ISCAS) IEEE International Symposium on Circuits and Systems (ISCAS) US ELECTR NETWORK 2020-10-10 2020 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) 000696570700071