Baek, Ji-Min Kim, Hyo-Jin Yoo, Ji-Hoon Shin, Ju-Won Shin, Ki-Yong Amir, Walid Ju, Gunwu Kim, Hyung-Jun Oh, Joohee Kim, Hyoungsub Kim, Tae-Woo Kim, Dae-Hyun 2024-01-19T10:33:58Z 2024-01-19T10:33:58Z 2023-02-17 2022-11 0038-1101 https://pubs.kist.re.kr/handle/201004/114281 In this work, we successfully fabricated vertical homo-junction In0.53Ga0.47As tunneling field-effect transistors (TFETs) by a top-down approach. We particularly focused on recovery of the sidewall damage induced during dry etching of the In0.53Ga0.47As layer. The recovery steps comprised a series of digital etching cycles, short wet etching of the In0.53Ga0.47As layer, and (NH4)(2)S-based treatment. The fabricated device with a gate length of 100 nm exhibited a minimum subthreshold swing of 52 mV/decade at room temperature and an average sub-threshold swing of 60 mV/decade over more than two decades of drain current. We also fabricated and analyzed In0.53Ga0.47As metal-oxidesemiconductor capacitors and metal-oxidesemiconductor field-effect transistors to investigate the effect of the S-treatment on their electrical characteristics. English Pergamon Press Ltd. Vertical homo-junction In0.53Ga0.47As tunneling field-effect transistors with minimum subthreshold swing of 52 mV/decade Article 10.1016/j.sse.2022.108447 1 Solid-State Electronics, v.197 Solid-State Electronics 197 N scie scopus 000911787200005 2-s2.0-85137607526 Engineering, Electrical & Electronic Physics, Applied Physics, Condensed Matter Engineering Physics Article In0 53Ga0 47As Tunneling field-effect transistors Vertical Top-down Plasma damage Surface recovery Sulfur treatment Sub-60mV decade