Jeong, Doo Seok Kornijcuk, Vladimir 2024-01-19T10:38:37Z 2024-01-19T10:38:37Z 2022-02-28 2018-07 2161-4393 https://pubs.kist.re.kr/handle/201004/114352 A look-up table (LUT)-based spike-routing approach is often used in inference-only neuromorphic systems due to its excellent reconfigurability. The challenge is to apply this approach also to on-chip learning that requires a search of a lengthy LUT for all relevant synapses to a firing neuron. To solve this issue, we propose a pointer-based routing scheme that remarkably accelerates spike-routing at the cost of an additional LUT (pointer LUT). Our theoretical estimations suggest that the proposed routing scheme at 1 GHz clock speed supports a spiking neural network of up to 10(7) synapses and more than 10(5) neurons firing at 50 Hz without spike traffic congestion. The scheme needs approximately 32 MB memory. To verify experimentally, the proposed routing scheme was implemented on a Xilinx Virtex 7 FPGA board deploying an array of leaky integrate-and-fire neurons. English IEEE Pointer Based Routing Scheme for On-chip Learning in Neuromorphic Systems Conference 1 International Joint Conference on Neural Networks (IJCNN), pp.451 - 456 International Joint Conference on Neural Networks (IJCNN) 451 456 US Rio de Janeiro, BRAZIL 2018-07-08 2018 INTERNATIONAL JOINT CONFERENCE ON NEURAL NETWORKS (IJCNN) 000585967400061