Kim, Seong Kwang Shim, Jaephil Geum, Dae-Myeong Kim, Chang Zoo Kim, Han-Sung Kim, Yeon-Su Kim, Sang Hyeon Song, Jin Dong Choi, Sung-Jin Kim, Dae Hwan Choi, Won Jun Kim, Hyung-jun Kim, Dong Myong Kang, Hang-Kyu 2024-01-19T11:09:13Z 2024-01-19T11:09:13Z 2022-03-01 2016-12 2380-9248 https://pubs.kist.re.kr/handle/201004/114684 Defect-less semiconductor-on-insulator (-OI) by a cost-effective and low temperature process is strongly needed for monolithic 3D (M3D) integration. Toward this, in this paper, we present a cost-effective fabrication of the InGaAs01 structure featuring the direct wafer bonding (DWB) and the epitaxial lift-off (ELO) techniques as well as the re-use of the InP donor wafer. We systematically investigated the effects of the pre-patterning of the III-V layer before DWB, surface reforming (hydrophilic), and electro-chemical etching to speed up the ELO process for a fast and high-throughput process, which is essential for cost reduction. We also demonstrated the re-usability of the InP donor wafer. Finally, as a result of the high film quality of the InGaAs channel combined with DWB and ELO, fabricated InGaAs-OI MOSFETs show a record high effective mobility of similar to 2800 cm(2)/Vs among surface channel In0.53Ga0.47As MOSFETs reported so far. English IEEE Cost-effective Fabrication of In0.53Ga0.47As-on-Insulator on Si for Monolithic 3D via Novel Epitaxial Lift-Off (ELO) and Donor Wafer Re-use Conference 1 62nd Annual IEEE International Electron Devices Meeting (IEDM) 62nd Annual IEEE International Electron Devices Meeting (IEDM) US San Francisco, CA 2016-12-03 2016 IEEE INTERNATIONAL ELECTRON DEVICES MEETING (IEDM) 000399108800154