Geum, Dae-Myeong Kim, Seong Kwang Lim, Hyeong-Rak Park, Juhyuk Jeong, Jaeyong Han, Jae Hoon Choi, Won Jun Kim, Hyo-Jin Kim, Sanghyeon 2024-01-19T14:32:34Z 2024-01-19T14:32:34Z 2021-09-05 2021-06 0741-3106 https://pubs.kist.re.kr/handle/201004/116925 We systematically investigated the wafer- bonded interfaces of p(+)GaAs/n(+)InGaAs and p(+)InGaAs/ n(+)InGaAs by using a circular transmission line method (CTLM) for the increased extraction accuracy. Based on the low-temperature bonding process at 50 degrees C, the bonded interfaces were successfully fabricated without degradation of the material quality. While the fabricated devices exhibited the linearly increased resistance as a function of channel distances, the p(+)InGaAs/n(+)InGaAs structure revealed the improved interfacial resistivity of 3.9 x 10(-3) Omega center dot cm(2) compared with 3.3x10(-2) Omega center dot cm(2) of the p(+)GaAs/n(+)InGaAs. Since these values suggested good electrical properties in wafer-bonded structures, the developed wafer-bonded interfaces could be a good approach for integrating electronic and optoelectronic devices. English IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC GAAS SOLAR-CELL SI RESISTANCE CONTACTS MODEL Electrical Analysis for Wafer-Bonded Interfaces of p(+)GaAs/n(+)InGaAs and p(+)InGaAs/n(+)InGaAs Article 10.1109/LED.2021.3076817 1 IEEE ELECTRON DEVICE LETTERS, v.42, no.6, pp.800 - 803 IEEE ELECTRON DEVICE LETTERS 42 6 800 803 scie scopus 000652794800005 2-s2.0-85105078350 Engineering, Electrical & Electronic Engineering Article GAAS SOLAR-CELL SI RESISTANCE CONTACTS MODEL Wafer bonding p(+)GaAs/n(+)InGaAs p(+)InGaAs/n(+)InGaAs