Jeon, Dae-Young Mouis, Mireille Barraud, Sylvain Ghibaudo, Gerard 2024-01-19T14:33:01Z 2024-01-19T14:33:01Z 2021-09-04 2021-06 0018-9383 https://pubs.kist.re.kr/handle/201004/116950 Junctionless transistors (JLTs) have promising advantages such as structural simplicity without p-n-junctions and bulk conduction-based operation for the realization of advanced complementary metal oxide semiconductor (CMOS) technologies. Here the channel-length dependence on the operation of JLTs with substrate biasing (V-gb) was investigated in detail. Parasitic series resistance (R-sd) noticeably decreased as V-gb increased. In addition, transconductance (g(m)), its derivative (dg(m)/dV(gf)), and ON-drain current (I-ON) in a short-channel JLT were significantly affected by the V-gb-modulated R-sd with charge coupling effects. This work provides important information for better understanding and true estimation of intrinsic JLT performance, for practical applications based on polycrystalline Si, III-V semiconductors, and transition metal dichalcogenides (TMDs) nano-materials as well as advanced logic devices. English IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC NANOWIRE TRANSISTORS SOI Impact of Channel Length on the Operation of Junctionless Transistors With Substrate Biasing Article 10.1109/TED.2021.3069936 1 IEEE TRANSACTIONS ON ELECTRON DEVICES, v.68, no.6, pp.3070 - 3073 IEEE TRANSACTIONS ON ELECTRON DEVICES 68 6 3070 3073 scie scopus 000652799800075 2-s2.0-85103908187 Engineering, Electrical & Electronic Physics, Applied Engineering Physics Article NANOWIRE TRANSISTORS SOI Transistors Substrates Resistance Silicon Logic gates Transconductance Charge carriers Channel-length dependence electrical parameters modulated by substrate bias junctionless transistors (JLTs) series resistance (Rsd) substrate-biasing effect