Jeon, Dae-Young Park, So Jeong Pregl, Sebastian Mikolajick, Thomas Weber, Walter M. 2024-01-19T15:03:50Z 2024-01-19T15:03:50Z 2021-09-05 2021-03-28 0021-8979 https://pubs.kist.re.kr/handle/201004/117245 The implementation of advanced electronic devices in the fourth industrial revolution era can be achieved with bottom-up grown silicon nanowire (Si-NW) based transistors. Here, we have fabricated reconfigurable Schottky-barrier (SB) thin-film transistors (TFTs) consisting of a parallel array of bottom-up grown single-crystalline Si-NWs and investigated in detail their device length dependent electrical performance and transport mechanism with current-voltage transport-map, key electrical parameters, and numerical simulation. In particular, the effective extension length (L-ext_eff) limited significantly the overall conduction behavior of reconfigurable Si-NW SB-TFTs, such as ambipolarity, mobility, threshold voltage, and series resistance. This work provides important information for a better understanding of the physical operation of reconfigurable transistors with SB contacts and further optimization of their performance for implementing practical applications. English AMER INST PHYSICS Reconfigurable thin-film transistors based on a parallel array of Si-nanowires Article 10.1063/5.0036029 1 JOURNAL OF APPLIED PHYSICS, v.129, no.12 JOURNAL OF APPLIED PHYSICS 129 12 scie scopus 000634945700003 2-s2.0-85103370613 Physics, Applied Physics Article Si nanowire Reconfigurable thin-film transistors ambipolar transistors Schottky-barrier current？voltage contour map