Lim, Hyeong-Rak Kim, Seong Kwang Han, Jae-Hoon Kim, Hansung Geum, Dae-Myeong Lee, Yun-Joong Ju, Byeong-Kwon Kim, Hyung-Jun Kim, Sanghyeon 2024-01-19T19:30:24Z 2024-01-19T19:30:24Z 2021-09-05 2019-09 0741-3106 https://pubs.kist.re.kr/handle/201004/119613 In this letter, we have fabricated Ge-on-insulator (Ge-OI) junctionless (JL) n-MOSFETs via wafer bonding and epitaxial lift-off (ELO) techniques. We have evaluated the electrical characteristics of Ge-OI JL n-MOSFETs with different thickness of Ge channel carefully thinned by the digital etching. Furthermore, the impact of bottom-gate biasing on the Ge-OI JL n-MOSFET devices with different Ge channel thicknesses has been demonstrated. High effective electron mobility (mu(eff)) of 160 cm(2)/V.s was obtained from a Ge-OI JL n-MOSFET with an 18 nm-thick Ge channel and subthreshold slope (S.S.) of 230 mV/dec was extracted on an even thinner 10-nm-thick Ge-OI JL n-MOSFET. Also, due to the stronger coupling between the channel and bottom-gate, we demonstrated higher Vth tunability and improvement of mu(eff) by bottom-gate biasing. English IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC MOBILITY Impact of Bottom-Gate Biasing on Implant-Free Junctionless Ge-on- Insulator n-MOSFETs Article 10.1109/LED.2019.2931410 1 IEEE ELECTRON DEVICE LETTERS, v.40, no.9, pp.1362 - 1365 IEEE ELECTRON DEVICE LETTERS 40 9 1362 1365 scie scopus 000483014600005 2-s2.0-85083680964 Engineering, Electrical & Electronic Engineering Article MOBILITY Ge MOSFETs Ge-OI Ge-on-Insulator junctionless MOSFETs wafer bonding epitaxial lift-off