Kwon, Sehyun Navarro, Carlos Gamiz, Francisco Cristoloveanu, Sorin Galy, Phileppe Choi, Minho Kim, Yong Tae Ahn, Jinho 2024-01-19T20:30:20Z 2024-01-19T20:30:20Z 2021-09-02 2019-04-01 0021-4922 https://pubs.kist.re.kr/handle/201004/120121 The electrical characteristics of band modulation FET are investigated with energy band diagrams between drain to source through intrinsic gate region according to front/back gates and drain bias conditions. The drain current-voltage and transfer characteristics show extremely steep slope with minimum subthreshold swing of 1.6 mV/decade. Memory window is 0.27 V, which is determined with turn on voltages at "0" and "1" states through multiple cycles of write and read operations. Memory performance also shows that current margin to distinguish the "0" and "1" state has the maximum value of over 100 mu A at V-D of 1.2 V. But, the current margin is relatively less affected by the front and back gate bias under the conditions that V-D is applied in the memory window range and the current at "0" state remains low. (C) 2019 The Japan Society of Applied Physics English IOP PUBLISHING LTD MOS I-MOS IMPACT-IONIZATION LOW-POWER CAPACITORLESS 1T-DRAM NEGATIVE CAPACITANCE PERFORMANCE TRANSISTORS CHANNEL MOSFETS FDSOI Characteristics of band modulation FET on sub 10 nm SOI Article 10.7567/1347-4065/aafc9f 1 JAPANESE JOURNAL OF APPLIED PHYSICS, v.58 JAPANESE JOURNAL OF APPLIED PHYSICS 58 scie scopus 000464309900030 2-s2.0-85065463361 Physics, Applied Physics Article MOS I-MOS IMPACT-IONIZATION LOW-POWER CAPACITORLESS 1T-DRAM NEGATIVE CAPACITANCE PERFORMANCE TRANSISTORS CHANNEL MOSFETS FDSOI band modulation 1T DRAM Steep swing slope Memory window Current margin