Marquez, Carlos Navarro, Carlos Navarro, Santiago Padilla, Jose L. Donetti, Luca Sampedro, Carlos Galy, Philippe Kim, Yong-Tae Gamiz, Francisco 2024-01-19T21:00:43Z 2024-01-19T21:00:43Z 2021-09-05 2019-02 2169-3536 https://pubs.kist.re.kr/handle/201004/120391 This paper addresses the low-frequency noise characterization of Z(2)-FET structures. These double-gated p-i-n diode devices have been fabricated at STMicroelectronics in an ultrathin body and box (UTBB) 28-nm FDSOI technology and designed to operate as 1T-DRAM memory cells, although other applications, as for example electro static discharge (ESD) protection, have been reported. The experimentally extracted power spectral density of current reveals that the high-diode series resistance, carrier number fluctuations due to oxide traps, and gate leakage current are the main noise contributors at high-current regimes. These mechanisms are expected to contribute to the degradation of cell variability and retention time. Higher flicker noise levels have been reported when increasing the vertical electric field. A simple model considering the contribution of the main noise sources is proposed. English IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC MECHANISMS OPERATION On the Low-Frequency Noise Characterization of Z(2)-FET Devices Article 10.1109/ACCESS.2019.2907062 1 IEEE ACCESS, v.7, pp.42551 - 42556 IEEE ACCESS 7 42551 42556 scie scopus 000465622600001 2-s2.0-85064825961 Computer Science, Information Systems Engineering, Electrical & Electronic Telecommunications Computer Science Engineering Telecommunications Article MECHANISMS OPERATION 1T-DRAM noise measurement p-i-n diodes semiconductor device reliability silicon on insulator technology Z(2)-FET