Jeon, Dae-Young Park, So Jeong Mouis, Mireille Barraud, Sylvain Kim, Gyu-Tae Ghibaudo, Gerard 2024-01-19T22:01:48Z 2024-01-19T22:01:48Z 2021-09-03 2018-09 0741-3106 https://pubs.kist.re.kr/handle/201004/120982 Junction less transistors (JLTs) without PN-junctions near the source/drain are promising candidates for further development of CMOS technology. The Si thickness of tri-gate JLTs is crucial to understand their unique electrical properties related to bulk neutral and surface accumulation conduction. A simple method based on a unique operation mechanism is suggested for extraction of t(si) from measurements on tri-gate JLTs. The method was successfully applied to fabricated tri-gate JLTs and the extracted t(si) values were comparable with those of transmission electron microscopy. Furthermore, the validity of the method was confirmed by 2-D numerical simulation. English IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC NANOWIRE TRANSISTORS CHANNEL WIDTH A Simple Method for Estimation of Silicon Film Thickness in T-Gate Junction less Transistors Article 10.1109/LED.2018.2857623 1 IEEE ELECTRON DEVICE LETTERS, v.39, no.9, pp.1282 - 1285 IEEE ELECTRON DEVICE LETTERS 39 9 1282 1285 scie scopus 000443054700003 2-s2.0-85050204994 Engineering, Electrical & Electronic Engineering Article NANOWIRE TRANSISTORS CHANNEL WIDTH Junctionless transistors (JLTs) Si thickness (t(si)) bulk neutral channel surface accumulation channel method for parameter extraction numerical simulation