Kim, Sang-Hyeon Kim, Seong-Kwang Shim, Jae-Phil Geum, Dae-Myeong Ju, Gunwu Kim, Han-Sung Lim, Hee-Jeong Lim, Hyeong-Rak Han, Jae-Hoon Lee, Subin Kim, Ho-Sung Bidenko, Pavlo Kang, Chang-Mo Lee, Dong-Seon Song, Jin-Dong Choi, Won Jun Kim, Hyung-Jun 2024-01-19T23:00:19Z 2024-01-19T23:00:19Z 2021-09-03 2018-05 2168-6734 https://pubs.kist.re.kr/handle/201004/121402 Monolithic 3-D integration has emerged as a promising technological solution for traditional transistor scaling limitations and interconnection bottleneck. The challenge we must overcome is a processing temperature limit for top side devices in order to ensure proper performance of bottom side devices. To solve this problem, we developed a low temperature III-V and Ge layer stacking process using wafer bonding and epitaxial lift-off, since these materials can be processed at a low temperature and provide extended opportunity/functionality (sensor, display, analog, RF, etc.) via heterogeneous integration. In this paper, we discuss technology for integrating III-V and Ge materials and its applicability to CMOS, thin film photodiodes, mid-infrared photonics platforms, and MicroLED display integration for creating the ultimate 3-D chip of the future. English IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC SI SUBSTRATE MIDINFRARED PHOTONICS SILICON FABRICATION Heterogeneous Integration Toward a Monolithic 3-D Chip Enabled by III-V and Ge Materials Article 10.1109/JEDS.2018.2802840 1 IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, v.6, no.1, pp.579 - 587 IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY 6 1 579 587 scie scopus 000435505000006 2-s2.0-85041506010 Engineering, Electrical & Electronic Engineering Article SI SUBSTRATE MIDINFRARED PHOTONICS SILICON FABRICATION Heterogeneous integration monolithic 3D sequential 3D layer transfer wafer bonding epitaxial lift-off III-V-OI GOI thin film PD mid-IR photonics microLED