Shim, Jae-Phil Kim, Seong Kwang Kim, Hansung Ju, Gunwu Lim, Heejeong Kim, SangHyeon Kim, Hyung-jun 2024-01-19T23:34:05Z 2024-01-19T23:34:05Z 2021-09-03 2018-01 2166-532X https://pubs.kist.re.kr/handle/201004/121858 We demonstrated ultra-thin-body (UTB) junctionless (JL) p-type field-effect transistors (pFETs) on Si using GaAs channels. Wafer bonding and epitaxial lift-off techniques were employed to fabricate the UTB p-GaAs-on-insulator on a Si template. Subsequently, we evaluated the JL FETs having different p-GaAs channel thicknesses considering both maximum depletion width and doping concentration for high performance. Furthermore, by introducing a double-gate operation, we more effectively controlled threshold voltage and attained an even higher I-ON/I-OFF of > 10(6), as well as a low subthreshold swing value of 300 mV/dec. (c) 2018 Author(s). English AMER INST PHYSICS TRANSISTORS TRANSPORT MOSFETS WAFER Double-gated ultra-thin-body GaAs-on-insulator p-FETs on Si Article 10.1063/1.5000532 1 APL MATERIALS, v.6, no.1 APL MATERIALS 6 1 scie scopus 000423723700004 2-s2.0-85040567705 Nanoscience & Nanotechnology Materials Science, Multidisciplinary Physics, Applied Science & Technology - Other Topics Materials Science Physics Article TRANSISTORS TRANSPORT MOSFETS WAFER GaAs double-gate Wafer bonding Epitaxial lift-off junctionless ultra-thin-body p-FET