Navarro, Carlos Duan, Meng Parihar, Mukta Singh Adamu-Lema, Fikru Coseman, Stefan Lacord, Joris Lee, Kyunghwa Sampedro, Carlos Cheng, Binjie El Dirani, Hassan Barbe, Jean-Charles Fonteneau, Pascal Kim, Seong-Il Cristoloveanu, Sorin Bawedin, Maryline Millar, Campbell Galy, Philippe Le Royer, Cyrille Karg, Siegfried Riel, Heike Wells, Paul Kim, Yong-Tae Asenov, Asen Gamiz, Francisco 2024-01-20T00:02:29Z 2024-01-20T00:02:29Z 2021-09-03 2017-12 0018-9383 https://pubs.kist.re.kr/handle/201004/122020 2-D numerical simulations are used to demonstrate the Z(2)-FET as a competitive embedded capacitor-less dynamic random access memory cell for low-power applications. Experimental results in 28-nm fully depleted-silicon on insulator technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption and integration density with other eDRAM cells in the literature. English IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC OPERATION 1T-DRAM Z(2)-FET as Capacitor-Less eDRAM Cell For High-Density Integration Article 10.1109/TED.2017.2759308 1 IEEE TRANSACTIONS ON ELECTRON DEVICES, v.64, no.12, pp.4904 - 4909 IEEE TRANSACTIONS ON ELECTRON DEVICES 64 12 4904 4909 scie scopus 000417727500014 2-s2.0-85032741002 Engineering, Electrical & Electronic Physics, Applied Engineering Physics Article OPERATION 1T-DRAM 1T-dynamic random access memory (DRAM) capacitor less DRAM embedded fully depleted (FD) integration low power scaling silicon on insulator (SOI) and Z(2)-FET