Navarro, Carlos Lacord, Joris Parihar, Mukta Singh Adamu-Lema, Fikru Duan, Meng Rodriguez, Noel Cheng, Binjie El Dirani, Hassan Barbe, Jean-Charles Fonteneau, Pascal Bawedin, Maryline Millar, Campbell Galy, Philippe Le Royer, Cyrille Karg, Siegfried Wells, Paul Kim, Yong-Tae Asenov, Asen Cristoloveanu, Sorin Gamiz, Francisco 2024-01-20T00:04:45Z 2024-01-20T00:04:45Z 2021-09-03 2017-11 0018-9383 https://pubs.kist.re.kr/handle/201004/122143 The Z(2)-FET operation as capacitorless DRAM is analyzed using advanced 2-D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28-nm fully depleted silicon-on-insulator devices. It is found that the triggering mechanism is dominated by the front-gate bias and the carrier's diffusion length. As in other FB-DRAMs, the memory window is defined by the ON voltage shift with the stored body charge. However, the Z(2)-FET's memory state is not exclusively defined by the inner charge but also by the reading conditions. English IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC 1T-DRAM Extended Analysis of the Z(2)-FET: Operation as Capacitorless eDRAM Article 10.1109/TED.2017.2751141 1 IEEE TRANSACTIONS ON ELECTRON DEVICES, v.64, no.11, pp.4486 - 4491 IEEE TRANSACTIONS ON ELECTRON DEVICES 64 11 4486 4491 scie scopus 000413732500017 2-s2.0-85030633174 Engineering, Electrical & Electronic Physics, Applied Engineering Physics Article 1T-DRAM 1T-DRAM capacitorless feedback effect fully depleted (FD) ground plane lifetime sharp switch silicon-on-insulator (SOI) Z(2)-FET