Kim, Gun Hwan Ju, Hyunsu Yang, Min Kyu Lee, Dong Kyu Choi, Ji Woon Jang, Jae Hyuck Lee, Sang Gil Cha, Ik Su Park, Bo Keun Han, Jeong Hwan Chung, Taek-Mo Kim, Kyung Min Hwang, Cheol Seong Lee, Young Kuk 2024-01-20T00:04:53Z 2024-01-20T00:04:53Z 2021-09-03 2017-10-25 1613-6810 https://pubs.kist.re.kr/handle/201004/122149 The quadruple-level cell technology is demonstrated in an Au/Al2O3/HfO2/TiN resistance switching memory device using the industry-standard incremental step pulse programming (ISPP) and error checking/correction (ECC) methods. With the highly optimistic properties of the tested device, such as self-compliance and gradual set-switching behaviors, the device shows 6s reliability up to 16 states with a state current gap value of 400 nA for the total allowable programmed current range from 2 to 11 mu A. It is demonstrated that the conventional ISPP/ECC can be applied to such resistance switching memory, which may greatly contribute to the commercialization of the device, especially competitively with NAND flash. A relatively minor improvement in the material and circuitry may enable even a five-bits-per-cell technology, which can hardly be imagined in NAND flash, whose state-of-the-art multiple-cell technology is only at three-level (eight states) to this day. English WILEY-V C H VERLAG GMBH THERMAL AGITATION MEMORY DIODE COST Four-Bits-Per-Cell Operation in an HfO2-Based Resistive Switching Device Article 10.1002/smll.201701781 1 SMALL, v.13, no.40 SMALL 13 40 scie scopus 000413416400006 2-s2.0-85032855933 Chemistry, Multidisciplinary Chemistry, Physical Nanoscience & Nanotechnology Materials Science, Multidisciplinary Physics, Applied Physics, Condensed Matter Chemistry Science & Technology - Other Topics Materials Science Physics Article THERMAL AGITATION MEMORY DIODE COST error checking/correction (ECC) algorithm HfO2 incremental step pulse programming (ISPP) quadruple-level cell (QLC) resistive switching (RS) memory