El Dirani, H. Lee, K. H. Parihar, M. S. Lacord, J. Martinie, S. Barbe, J-Ch. Mescot, X. Fonteneau, P. Broquin, J. -E. Ghibaudo, G. Galy, Ph Gamiz, F. Taur, Y. Kim, Y. -T. Cristoloveanu, S. Bawedin, M. 2024-01-20T01:04:18Z 2024-01-20T01:04:18Z 2021-09-05 2017-06-25 0167-9317 https://pubs.kist.re.kr/handle/201004/122613 A systematic study of a capacitorless 1T-DRAM fabricated in 28 nm FDSOI technology is presented. The operation mechanism is based on band modulation. The Z(2)-FET memory cell features a large current sense margin and small OFF-state current at 25 degrees C and 85 degrees C. Moreover, low power consumption during state '1' writing is achieved with similar to 0.5 V programming voltage. These specifications make the Z(2)-FET an outstanding candidate for low-power eDRAM applications. (C) 2017 Elsevier B.V. All rights reserved. English ELSEVIER CAPACITORLESS 1T-DRAM GATE Z(2)-FET DEVICES Ultra-low power 1T-DRAM in FDSOI technology Article 10.1016/j.mee.2017.05.047 1 MICROELECTRONIC ENGINEERING, v.178, pp.245 - 249 MICROELECTRONIC ENGINEERING 178 245 249 scie scopus 000404703800056 2-s2.0-85019871691 Engineering, Electrical & Electronic Nanoscience & Nanotechnology Optics Physics, Applied Engineering Science & Technology - Other Topics Optics Physics Article; Proceedings Paper CAPACITORLESS 1T-DRAM GATE Z(2)-FET DEVICES Fully Depleted Silicon-On-Insulator (FDSOI) Sharp switch Z(2)-FET Low-power Embedded memory 1T-DRAM