Im, Ki-Sik Won, Chul-Ho Vodapally, Sindhuri Caulmilone, Raphael Cristoloveanu, Sorin Kim, Yong-Tae Lee, Jung-Hee 2024-01-20T03:04:02Z 2024-01-20T03:04:02Z 2021-09-05 2016-10-03 0003-6951 https://pubs.kist.re.kr/handle/201004/123576 Lateral GaN nanowire gate-all-around transistor has been fabricated with top-down process and characterized. A triangle-shaped GaN nanowire with 56 nm width was implemented on the GaN-on-insulator (GaNOI) wafer by utilizing (i) buried oxide as sacrificial layer and (ii) anisotropic lateral wet etching of GaN in tetramethylammonium hydroxide solution. During subsequent GaN and AlGaN epitaxy of source/drain planar regions, no growth occurred on the nanowire, due to self-limiting growth property. Transmission electron microscopy and energy-dispersive X-ray spectroscopy elemental mapping reveal that the GaN nanowire consists of only Ga and N atoms. The transistor exhibits normally-off operation with the threshold voltage of 3.5V and promising performance: the maximum drain current of 0.11mA, the maximum transconductance of 0.04 mS, the record off-state leakage current of similar to 10(-13) A/mm, and a very high I-on/I-off ratio of 10(8). The proposed top-down device concept using the GaNOI wafer enables the fabrication of multiple parallel nanowires with positive threshold voltage and is advantageous compared with the bottom-up approach. Published by AIP Publishing. English AMER INST PHYSICS PERFORMANCE TRANSISTORS Fabrication of normally-off GaN nanowire gate-all-around FET with top-down approach Article 10.1063/1.4964268 1 APPLIED PHYSICS LETTERS, v.109, no.14 APPLIED PHYSICS LETTERS 109 14 scie scopus 000386152800049 2-s2.0-84989828252 Physics, Applied Physics Article PERFORMANCE TRANSISTORS GaN Nano-wire gate all around FET (GAA) GaN on Insulator Normally off high performance High power