Kim, SangHyeon Geum, Dae-Myeong Kim, Seong Kwang Kim, Hyung-Jun Song, Jin Dong Choi, Won Jun 2024-01-20T03:04:30Z 2024-01-20T03:04:30Z 2021-09-05 2016-10 0741-3106 https://pubs.kist.re.kr/handle/201004/123603 In this letter, we have demonstrated low-subthreshold-slope (SS) asymmetric double-gate (DG) GaAs-oninsulator field-effect-transistors (FETs) on Si substrates via wafer bonding and epitaxial liftoff techniques. We found that DG FETs show lower SS than single-gate FETs all over the range of the drain current. A minimum value of SS was 68 mV/decade, which is very close to the theoretical limit. In addition, the achieved SS value was a record-low among the reported GaAs transistors so far. English IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC CHANNEL MOSFETS SILICON Low-Subthreshold-Slope Asymmetric Double-Gate GaAs-on-Insulator Field-Effect-Transistors on Si Article 10.1109/LED.2016.2601081 1 IEEE ELECTRON DEVICE LETTERS, v.37, no.10, pp.1261 - 1263 IEEE ELECTRON DEVICE LETTERS 37 10 1261 1263 scie scopus 000385371100001 2-s2.0-84989837206 Engineering, Electrical & Electronic Engineering Article CHANNEL MOSFETS SILICON GaAs FETs double-gate GaAS-OI wafer bonding epitaxial lift-off