Kim, Seong Kwang Lee, Jungmin Geum, Dae-Myeong Park, Min-Su Choi, Won Jun Choi, Sung-Jin Kim, Dae Hwan Kim, Sanghyeon Kim, Dong Myong 2024-01-20T03:34:27Z 2024-01-20T03:34:27Z 2021-09-04 2016-08 0038-1101 https://pubs.kist.re.kr/handle/201004/123840 We report characterization of the interface trap distribution (D-it(E)) over the bandgap in III-V metal-oxide- semiconductor field-effect transistors (MOSFETs) on insulator. Based only on the experimental subthreshold current data and differential coupling factor, we simultaneously obtained D-it(E) and a nonlinear mapping of the gate bias (V-GS) to the trap level (E-t) via the effective surface potential (psi(S),(eff)). The proposed technique allows direct extraction of the interface traps at the In0.53Ga0.47As-on insulator (-OI) MOSFETs only from the experimental subthreshold current data. Applying the technique to the In0.53Ga0.47As channel III-V-OI MOSFETs with the gate width/length W/L = 100/50, 100/25, and 100/10 mu m/mu m, we obtained D-it(E) congruent to 10(11)-10(12) eV(-1) cm(-2) over the bandgap without the dimension dependence. (C) 2016 Elsevier Ltd. All rights reserved. English PERGAMON-ELSEVIER SCIENCE LTD OXIDE INTERFACE STATES Fully subthreshold current-based characterization of interface traps and surface potential in III-V-on-insulator MOSFETs Article 10.1016/j.sse.2016.04.011 1 SOLID-STATE ELECTRONICS, v.122, pp.8 - 12 SOLID-STATE ELECTRONICS 122 8 12 scie scopus 000376199800002 2-s2.0-84966304370 Engineering, Electrical & Electronic Physics, Applied Physics, Condensed Matter Engineering Physics Article OXIDE INTERFACE STATES Interface trap InGaAs-OI MOSFETs III-V Subthreshold current model