Kim, Ju Eon Cho, Seong-Jin Kim, Yong Sin Lee, Seok Baek, Kwang-Hyun 2024-01-20T09:30:39Z 2024-01-20T09:30:39Z 2021-09-05 2014-07-31 0013-5194 https://pubs.kist.re.kr/handle/201004/126571 An energy-efficient capacitor switching digital-to-analogue converter (DAC) is proposed for successive-approximation register analogue-to-digital converters (SAR ADCs). The proposed charge-average switching with floating capacitors (CASFCs) DAC disconnects the most significant bit (MSB) capacitors from the capacitor array after determining the MSB. The switching energy of the proposed CASFC DAC is lower than that of the recently published DAC, because the CAS technique is only employed in the CASFC DAC, while both the traditional and CAS methods are used in the previous DAC depending on inputs. In addition, the energy during the reset period is also minimised because the floated MSB capacitors do not consume the reset energy. The CASFC DAC reduces the switching energy with and without reset by 64.4 and 37.5%, respectively, compared with the aforementioned previous DAC. English INST ENGINEERING TECHNOLOGY-IET Energy-efficient charge-average switching DAC with floating capacitors for SAR ADC Article 10.1049/el.2014.1792 1 ELECTRONICS LETTERS, v.50, no.16, pp.1131 - + ELECTRONICS LETTERS 50 16 1131 + scie scopus 000341023800015 2-s2.0-84905225435 Engineering, Electrical & Electronic Engineering Article ADC switching DAC SAR