Rha, Sang Ho Kim, Un Ki Jung, Jisim Hwang, Eun Suk Choi, Jung-Hae Hwang, Cheol Seong 2024-01-20T11:04:58Z 2024-01-20T11:04:58Z 2021-09-05 2013-10-28 0003-6951 https://pubs.kist.re.kr/handle/201004/127530 Two serially connected and vertically integrated amorphous-In2Ga2ZnO7 thin film transistors (V-TFTs) with similar to 600 and 400-nm channel lengths were fabricated. Top and bottom V-TFTs showed well-behaved transfer characteristics with an I-on/I-off ratio of similar to 10(8) and a sub-threshold swing of similar to 0.6 V/dec., which are much improved results compared with the previous report on single-layer V-TFTs. Electrical performances of two V-TFTs were cross-checked, and they showed certain influences from the other device depending on operation conditions, which was attributed to charge trapping in the gate dielectric layer during gate voltage sweeping. V-TFT with thermally grown SiO2 showed negligible charge trapping behavior. (C) 2013 AIP Publishing LLC. English AMER INST PHYSICS Double-layered vertically integrated amorphous-In2Ga2ZnO7 thin-film transistor Article 10.1063/1.4827955 1 APPLIED PHYSICS LETTERS, v.103, no.18 APPLIED PHYSICS LETTERS 103 18 scie scopus 000327816000078 2-s2.0-84889679838 Physics, Applied Physics Article