Jung, Hyung-Suk Yu, Il-Hyuk Kim, Hyo Kyeom Lee, Sang Young Lee, Joohwi Choi, Yujin Chung, Yoon Jang Lee, Nae-In Park, Tae Joo Choi, Jung-Hae Hwang, Cheol Seong 2024-01-20T14:03:29Z 2024-01-20T14:03:29Z 2021-09-04 2012-09 0018-9383 https://pubs.kist.re.kr/handle/201004/128940 The dielectric performance and charge trapping properties of HfO2 on a Ge substrate with various passivating interfacial layers (PILs), such as SiOxNy, AlOxNy, HfOxNy, and LaOxNy, are investigated. The large capacitance-voltage (C-V) hysteresis of HfO2 on a Ge substrate (similar to 1500 mV) was not improved by inserting either HfOxNy or LaOxNy PIL between the HfO2 and Ge substrates, while both SiOxNy and AlOxNy PILs induced a noticeable reduction of C-V hysteresis. As the PILs' thicknesses increased, the C-V hysteresis of HfO2 with SiOxNy PIL decreased to almost zero, while that of HfO2 with AlOxNy PIL decreased but was saturated at approximately 400 mV. Furthermore, the charge trapping property of HfO2 with SiOxNy PIL on a Ge substrate is comparable to that of HfO2 grown on a Si substrate. Negligible C-V hysteresis and negligible charge trapping of HfO2 with SiOxNy PIL were understood from the fact that SiOxNy is more resistant to react with a Ge substrate and defective Ge suboxides are efficiently suppressed during the formation of SiOxNy PIL and HfO2 layers. English IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC THERMAL-STABILITY GATE DIELECTRICS OXIDE CAPACITORS GE(100) Reduction of Charge Trapping in HfO2 Film on Ge Substrates by Atomic Layer Deposition of Various Passivating Interfacial Layers Article 10.1109/TED.2012.2204996 1 IEEE TRANSACTIONS ON ELECTRON DEVICES, v.59, no.9, pp.2350 - 2356 IEEE TRANSACTIONS ON ELECTRON DEVICES 59 9 2350 2356 scie scopus 000307905200012 2-s2.0-84865451609 Engineering, Electrical & Electronic Physics, Applied Engineering Physics Article THERMAL-STABILITY GATE DIELECTRICS OXIDE CAPACITORS GE(100) Atomic layer deposition (ALD) germanium (Ge) hafnium oxide (HfO2) high-k gate dielectrics passivation layer