Kim, Dongkyun Jung, Junhee Thuy Tuong Nguyen Kim, Daijin Kim, Munsang Kwon, Key Ho Jeon, Jae Wook 2024-01-20T14:34:21Z 2024-01-20T14:34:21Z 2021-09-04 2012-06 1598-1657 https://pubs.kist.re.kr/handle/201004/129225 Eye detection is widely used in applications, such as face recognition, driver behavior analysis, and human-computer interaction. However, it is difficult to achieve real-time performance with software-based eye detection in an embedded environment. In this paper, we propose a parallel hardware architecture for real-time eye detection. We use the AdaBoost algorithm with modified census transform(MCT) to detect eyes on a face image. We parallelize part of the algorithm to speed up processing. Several downscaled pyramid images of the eye candidate region are generated in parallel using the input face image. We can detect the left and the right eye simultaneously using these downscaled images. The sequential data processing bottleneck caused by repetitive operation is removed by employing a pipelined parallel architecture. The proposed architecture is designed using Verilog HDL and implemented on a Virtex-5 FPGA for prototyping and evaluation. The proposed system can detect eyes within 0.15 ms in a VGA image. English IEEK PUBLICATION CENTER DEFORMABLE TEMPLATES FEATURE-EXTRACTION FACE DETECTION TRACKING An FPGA-based Parallel Hardware Architecture for Real-time Eye Detection Article 10.5573/JSTS.2012.12.2.150 1 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.12, no.2, pp.150 - 161 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE 12 2 150 161 scie scopus kci ART001701847 000306799300005 2-s2.0-84863817418 Engineering, Electrical & Electronic Physics, Applied Engineering Physics Article DEFORMABLE TEMPLATES FEATURE-EXTRACTION FACE DETECTION TRACKING Eye detection hardware architecture FPGA image processing HDL