Jin, S. Cho, J. Pham, X. D. Lee, K. M. Park, S. -K. Kim, M. Jeon, J. W. 2024-01-20T20:02:39Z 2024-01-20T20:02:39Z 2021-09-05 2010-01 1051-8215 https://pubs.kist.re.kr/handle/201004/131810 Stereo vision is a well-known ranging method because it resembles the basic mechanism of the human eye. However, the computational complexity and large amount of data access make real-time processing of stereo vision challenging because of the inherent instruction cycle delay within conventional computers. In order to solve this problem, the past 20 years of research have focused on the use of dedicated hardware architecture for stereo vision. This paper proposes a fully pipelined stereo vision system providing a dense disparity image with additional sub-pixel accuracy in real-time. The entire stereo vision process, such as rectification, stereo matching, and post-processing, is realized using a single field programmable gate array (FPGA) without the necessity of any external devices. The hardware implementation is more than 230 times faster when compared to a software program operating on a conventional computer, and shows stronger performance over previous hardware-related studies. English IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC OCCLUSIONS FPGA Design and Implementation of a Real-Time Stereo Vision System Article 10.1109/TCSVT.2009.2026831 1 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, v.20, no.1, pp.15 - 26 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 20 1 15 26 scie scopus 000273566200004 2-s2.0-74249089027 Engineering, Electrical & Electronic Engineering Article OCCLUSIONS Field programmable gate arrays integrated circuit design stereo vision video signal processing