Lee, Dong Uk Lee, Min Seung Kim, Eun Kyu Koo, Hyun-Mo Cho, Won-Ju Kim, Won Mok 2024-01-20T21:32:49Z 2024-01-20T21:32:49Z 2021-09-01 2009-05 0374-4884 https://pubs.kist.re.kr/handle/201004/132550 Nonvolatile memory devices with double-stacked Au nano-crystals on p-type (100) silicon-on-insulator wafers were fabricated and the electrical characteristics, such as the subthreshold property, the threshold voltage shift and the retention property, were analyzed. Here, the Au nano-crystals, the SiO(1.3)N control and the tunnel oxides were deposited by reactive RF magnetron sputtering. The channel length and width of the nano-floating gate memory, which contained the double-stacked Au nano-crystals, were 20 mu m. The memory window was about 1.23 V when the programming and erasing times of this memory device were approximately 500 mu s and 5 ms, respectively. However, the memory window increased up to about 6 V when initial programming/erasing conditions were 20 V for 200 ms and -20 V for 500 ms and it was maintained at 2.7 V after 10(3) s. English KOREAN PHYSICAL SOC ELECTRICAL CHARACTERIZATION FLOATING-GATE PARTICLES Fabrication of a Nonvolatile Memory with Double-Stacked Au Nano-Crystals Article 10.3938/jkps.54.1824 1 JOURNAL OF THE KOREAN PHYSICAL SOCIETY, v.54, no.5, pp.1824 - 1828 JOURNAL OF THE KOREAN PHYSICAL SOCIETY 54 5 1824 1828 scie scopus kci ART001500881 000266093900011 2-s2.0-68049116823 Physics, Multidisciplinary Physics Article ELECTRICAL CHARACTERIZATION FLOATING-GATE PARTICLES Au Nano-floating gate memory SiON