Han, I. K. Nam, H. D. Choi, W. J. Lee, J. I. Szentpali, B. Chovet, A. 2024-01-21T02:33:26Z 2024-01-21T02:33:26Z 2021-09-01 2006-09 0374-4884 https://pubs.kist.re.kr/handle/201004/135218 The results of a simulation study on low-frequency excess noise in high-k SiO2/HfO2 dual dielectric n-MOSFETs are reported. Based on the 'Unified Model' where tunneling to traps in oxides is the major noise generation mechanism, we show how the low-frequency noise density and the frequency power index depend on the thickness of the interfacial oxide layer. Also, a simple and useful parameter extraction method for low-frequency noise is introduced. English KOREAN PHYSICAL SOC HFO2 Low-frequency noise in high-k gate dielectric nanoscale MOSFETs Article 1 JOURNAL OF THE KOREAN PHYSICAL SOCIETY, v.49, no.3, pp.1117 - 1120 JOURNAL OF THE KOREAN PHYSICAL SOCIETY 49 3 1117 1120 scie scopus kci ART001195857 000240570400057 2-s2.0-33749837876 Physics, Multidisciplinary Physics Article HFO2 1/f noise high-k dielectric MOSFETs tunneling