Shim, SII Kwon, YS Kim, SII Kim, YT Park, J.H. 2024-01-21T06:44:02Z 2024-01-21T06:44:02Z 2021-09-02 2004-07 0734-2101 https://pubs.kist.re.kr/handle/201004/137467 We have investigated an etch-stop process and fabricated the ferroelectric gate transistor without damage of source and drain regions using etching selectivity between etch rates of SrBi2Ta2O9 (SBT) and CeO2. The SBT and CeO2 were etched with inductively coupled plasma (ICP) reactive ion etching at various Ar/Cl-2 gas mixing ratios, ICP powers, and rf bias powers. The etching selectivity of SBT/CeO2 was 6.8 and the vertical etching angle of SBT was 82degrees at the condition of 50% Cl-2 concentration with the ICP power of 900 W and the rf bias power of 100 W. The characteristics of devices fabricated with an etch-stop process showed that there was no degradation of the ferroelectric characteristics and on/off ratio of programmable operation was 10(4). (C) 2004 American Vacuum Society. English A V S AMER INST PHYSICS Selective etching process of SrBi2Ta2O9 and CeO2 for self-aligned ferroelectric gate structure Article 10.1116/1.1701859 1 JOURNAL OF VACUUM SCIENCE & TECHNOLOGY A, v.22, no.4, pp.1559 - 1563 JOURNAL OF VACUUM SCIENCE & TECHNOLOGY A 22 4 1559 1563 scie scopus 000223322000081 2-s2.0-4444378360 Materials Science, Coatings & Films Physics, Applied Materials Science Physics Article; Proceedings Paper