Kim, YT Shin, DS Park, YK Choi, IH 2024-01-21T15:04:06Z 2024-01-21T15:04:06Z 2021-09-04 1999-09-15 0021-8979 https://pubs.kist.re.kr/handle/201004/141911 Interface morphology and electrical properties of Pt/SrBi2Ta2O9(SBT)/CeO2/Si ferroelectric gate structure are characterized by considering the interactions among Bi, O, and Pt atoms during annealing process. It is found that the interfacial roughness of the Pt/SBT might be reduced during the annealing at 800 degrees C because the bottom side of the Pt electrode reacts with Bi atoms outdiffused from the SBT and the Bi-Pt alloys are molten at 765 degrees C, and the metallic Bi atoms are consumed by forming Bi oxide. Additionally, the capacitance and memory window of the ferroelectric gate structure annealed at 800 degrees C decrease to 69% and 80% of those values of the as-deposited gate structure, respectively, due to the additional capacitance and the voltage drop at the low dielectric Bi-oxide capacitor. In contrast, the leakage current characteristics are improved by two orders of magnitude after annealing at 800 degrees C for 30 min. (C) 1999 American Institute of Physics. [S0021-8979(99)00418-1]. English AMER INST PHYSICS THIN-FILMS Effects of Bi-Pt alloy on electrical characteristics of Pt/SrBi2Ta2O9/CeO2/Si ferroelectric gate structure Article 10.1063/1.371218 1 JOURNAL OF APPLIED PHYSICS, v.86, no.6, pp.3387 - 3390 JOURNAL OF APPLIED PHYSICS 86 6 3387 3390 scie scopus 000082232400070 2-s2.0-0008839215 Physics, Applied Physics Article THIN-FILMS Bi-Pt alloy ferroelectric interfacial roughness